// **************************************************************
// Copyright (c) 2021 Xidian University.
// File name     : single_bus.v
// Module name   : 
// Created Date  : 2022-04
// Author        : Guowei/Xuyang
// Email         : 
// -------------------------------------------------------------------------
// Version       : 
// Last Modified : 2022-07-01 12:44:08
// Modified By   : Wangzekun
// -------------------------------------------------------------------------
// 
// -------------------------------------------------------------------------
// HISTORY       : v0.4
// Date         By  Comments
// ------------ --  ----------------------------------------------------------
// v0.1--Guowei/Xuyang
// v0.2--add scan_ME module and modify interface to suit 21 bit address
// v0.3--output ff_clk,modify module name to single_bus
// v0.4--add bus to cr bridge,for cpu access phy register
//
// **************************************************************
`include "top_define.v"
module single_bus #(
  // parameter frame_mac_dst_bus = 48'h1000_0000_0001,
  // parameter frame_mac_src_bus = 48'h1000_0000_0002,
  parameter frame_length_bus  = 16'h88b6
  // parameter CLUSTER_ID        = 2'b00
)
(
//param
  input   wire [47:0]   frame_mac_dst ,
  input   wire [47:0]   frame_mac_src ,
  input   wire  [1:0]   cluster_id    ,
//-------------------------------------------------------
// eth_mac_phy
//-------------------------------------------------------

//vss&vdd
  inout   wire          vp           ,    
  inout   wire          vpdig        ,
  inout   wire          vph          ,   
  inout   wire          vptx0        ,
  inout   wire          vptx1        ,
  inout   wire          vptx2        ,
  inout   wire          vptx3        , 
  inout   wire          vsscore_0    ,
  inout   wire          vsscore_1    ,
  inout   wire          vsscore_2    ,
  inout   wire          gd           ,
  
  //phy_mac_interface
  input  wire [16:0]    phy_ctrl_register  ,
  input  wire [25:0]    reset_register     ,
  input  wire [ 8:0]    req_lb_register    ,
  output wire [ 8:0]    ack_register_temp  ,//output在subsys与 np_reg_sync
  input  wire [11:0]    mac_pcs_status_register1,
  output wire [27:0]    mac_pcs_status_register0_temp,
  output wire [16:0]    mac_pcs_status_register2_temp,
  
  //jtag signals
  input  wire           jtag_tck              ,//jtag clk
  input  wire           jtag_tdi              ,
  output wire           jtag_tdo              ,
  output wire           jtag_tdo_en           ,//subsys中assign phy_jtag_tdi_1 = phy_jtag_tdo_0 && phy_jtag_tdo_en_0;
  input  wire           jtag_tms              ,
  input  wire           jtag_trst_n           ,
   
  //clk and clk_en
  inout  wire           ref_pad_clk_m         ,
  inout  wire           ref_pad_clk_p         , 
  input  wire           ref_alt_clk_m         ,
  input  wire           ref_alt_clk_p         ,
      
  //Resistor Tune Signals
  inout   wire          resref                ,
  
  //serial data signals
  input  wire           res_ack_in          ,
  output wire           res_ack_out         ,
  input  wire           res_req_in          ,
  output wire           res_req_out         ,
  
  inout  wire           rx0_m                 ,
  inout  wire           rx0_p                 ,
  inout  wire           rx1_m                 ,
  inout  wire           rx1_p                 ,
  inout  wire           rx2_m                 ,
  inout  wire           rx2_p                 ,
  inout  wire           rx3_m                 ,
  inout  wire           rx3_p                 ,
  
  inout  wire          tx0_m                ,
  inout  wire          tx0_p                ,
  inout  wire          tx1_m                ,
  inout  wire          tx1_p                ,
  inout  wire          tx2_m                ,
  inout  wire          tx2_p                ,
  inout  wire          tx3_m                ,
  inout  wire          tx3_p                ,
  
  //mac signals
  input  wire           ref_ff_clk_630plus    ,
  input  wire           reg_clk               ,
  
  input  wire           xpcs_reg_wren       ,
  input  wire           xpcs_reg_rden       ,
  input  wire [15:0]    xpcs_reg_addr       ,
  input  wire [15:0]    xpcs_reg_din        ,
  output wire [15:0]    xpcs_reg_dout       ,
  output wire           xpcs_reg_busy       ,
  
  input  wire           xlpcs_reg_wren      ,
  input  wire           xlpcs_reg_rden      ,
  input  wire [15:0]    xlpcs_reg_addr      ,
  input  wire [15:0]    xlpcs_reg_din       ,
  output wire [15:0]    xlpcs_reg_dout      ,
  output wire           xlpcs_reg_busy      ,
  
  input  wire           mac_reg_wren         ,
  input  wire           mac_reg_rden         ,
  input  wire [ 7:0]    mac_reg_addr        ,
  input  wire [31:0]    mac_reg_din         ,
  output wire [31:0]    mac_reg_dout        ,
  output wire           mac_reg_busy        ,
  input  wire           mac_reg_lowp_ena    ,            
  
  output wire [63:0]    mac_tx_ts           ,
  input  wire [63:0]    mac_frc_in_tx       ,
  input  wire [63:0]    mac_frc_in_rx       ,

//---------------------------------------------------------------
//fp_and_sch_top
//---------------------------------------------------------------
input               pkt_clk                     ,
input               pkt_rstn                    ,
output              fp_sch_init_done            ,//with jtag
input               hclk_i                      ,
input               hresetn_i                   ,

//with CPU config，with jtag
//ME1-ME6 ahb
input  wire [31:0]np_data_in     ,//with interface,原mac 100 top
input  wire [16:0]np_addr_in     ,
input  wire       np_wr_in       ,
input  wire       np_rd_in       ,
output reg  [31:0]np_data_out    ,//with jtag
output reg        bus_np_data_out_vld,//需要接入其他逻辑，间接接入fp

//input  wire [45:0]bus_np_addr_ctrl   ,

//with other bus's fp
//这里的bus1意味着从本条总线出去的信号，bus2-4指从其他bus进来的信号
output wire [9:0]   bus1_table_addr2            ,
output wire [9:0]   bus1_table_ram_addr_convert ,
output wire [71:0]  bus1_table_data2            ,
output wire [71:0]  bus1_table_ram_data_convert ,
output wire         bus1_table_wren2            ,
output wire         bus1_table_ram_wr_en_convert,
input  wire [9:0]   bus2_table_addr2            ,
input  wire [9:0]   bus2_table_ram_addr_convert ,
input  wire [71:0]  bus2_table_data2            ,
input  wire [71:0]  bus2_table_ram_data_convert ,
input  wire         bus2_table_wren2            ,
input  wire         bus2_table_ram_wr_en_convert,
input  wire [9:0]   bus3_table_addr2            ,
input  wire [9:0]   bus3_table_ram_addr_convert ,
input  wire [71:0]  bus3_table_data2            ,
input  wire [71:0]  bus3_table_ram_data_convert ,
input  wire         bus3_table_wren2            ,
input  wire         bus3_table_ram_wr_en_convert,
input  wire [9:0]   bus4_table_addr2            ,
input  wire [9:0]   bus4_table_ram_addr_convert ,
input  wire [71:0]  bus4_table_data2            ,
input  wire [71:0]  bus4_table_ram_data_convert ,
input  wire         bus4_table_wren2            ,
input  wire         bus4_table_ram_wr_en_convert,

//with crossbar
input wire          uni_tx_rdy00                ,
input wire          uni_tx_rdy01                ,
input wire          uni_tx_rdy02                ,
input wire          uni_tx_rdy03                ,
input wire          mul_tx_rdy00                ,
input wire          mul_tx_rdy01                ,
input wire          mul_tx_rdy02                ,
input wire          mul_tx_rdy03                ,

output  wire [255:0] emac_data_in              ,
output  wire         emac_data_wren            ,
output  wire [  5:0] rx_address_dpram          ,
output  wire [  3:0] mac_dest_port_in          ,
output  wire         mul_indicate              ,

input wire           pkt_sop_i     , // 和crossbar pkt_sop_o_0 相接的信号，接进来用于计数
input wire [255:0]   pkt_data_i    ,         
input wire           pkt_eop_i     ,                     
input wire [4:0]     pkt_mod_i     ,            
input wire           pkt_dval_i    ,

//---------------------------------------------------------------
//mac to np
//---------------------------------------------------------------
input [  9:0]   ram_2p_cfg_register,
input [ 11:0]   ram_dp_cfg_register,
input  [6:0]    rf_2p_cfg_register ,
`ifdef SIM

output wire         bus_axi_valid_o,
output wire [255:0] bus_axi_data_o,
output wire         bus_axi_last_o,
output wire [ 31:0] bus_axi_keep_o,
input  wire         bus_axi_ready_o,

input  wire         bus_axi_valid_i,
input  wire [255:0] bus_axi_data_i,
input  wire         bus_axi_last_i,
input  wire [ 31:0] bus_axi_keep_i,
output wire         bus_axi_ready_i,

`endif 

output              emac_rx_ready,//with crosssbar
output wire         ff_clk,

//---------------------------------------------------------------
//cpt to dma/dma channel sel , 2022.5.1 xym
//---------------------------------------------------------------
input  wire [  1:0] dma_channel_sel,
input  wire [  1:0] sel_dma_scope,
input  wire         dma_clk,
input  wire         dma_rstn,
input  wire         dma_rd_leng_en_i,
input  wire         dma_rd_data_en_i,
output wire         dma_rd_leng_vld_o,
output wire         dma_rd_dout_vld_o,
output wire [ 10:0] dma_rd_leng_o,
output wire [127:0] dma_rd_dout_o,
output wire         dma_empty_o,
output wire         dma_data_empty_o,//5.23 xym

input  wire         dma_axi_ttvalid ,
input  wire         dma_axi_ttlast  ,
input  wire [  7:0] dma_axi_ttkeep  ,
input  wire [ 63:0] dma_axi_ttdata  ,
output reg          dma_axi_ttready ,

output reg          dma_axi_rtvalid ,
output reg          dma_axi_rtlast  ,
output reg  [  7:0] dma_axi_rtkeep  ,
output reg  [ 63:0] dma_axi_rtdata  ,
input  wire         dma_axi_rtready ,

// DFT port
input  wire         testmode        ,
input  wire         se              ,
input  wire         phy_scan_clk    

);
//仅接线并未接入其他模块
  wire           clk_repeat_clk_m       ; 
  wire           clk_repeat_clk_p       ; 
  wire           phy_ref_dig_clk        ;
  reg      [7:0] src_node_id            ;

// MAC2NP
  wire           rx_rdy_mac             ;
  wire           ref_clk                ;
   
  wire          tx_axis_tvalid      ;
  wire [63:0]   tx_axis_tdata       ;
  wire          tx_axis_tlast       ;
  wire [ 7:0]   tx_axis_tkeep       ;
  // output [ 6:0]   tx_axis_tuser       ;
  wire           tx_axis_tready      ;

    //wire       pkt_clk           ;
    //wire       pkt_rstn           ;

    `ifdef SIM
       wire         axi_valid_o;
       wire [255:0] axi_data_o;
       wire         axi_last_o;
       wire [ 31:0] axi_keep_o;
       wire         axi_ready_o;

      wire         axi_valid_i;
      wire [255:0] axi_data_i;
      wire         axi_last_i;
      wire [ 31:0] axi_keep_i;
      wire         axi_ready_i;
    `endif

    wire pkt_test_sop;
    wire pkt_test_dvld;
    wire pkt_test_dsav;
    wire [255:0]pkt_test_data;
    wire pkt_test_eop;

    // wire np_bus_axi_ttready; // 2022.5.1 xym

wire        bus_ins_cpt_rd_vld  ;
wire [31:0] bus_ins_cpt_data_out ;
wire        bus_fp_sch_rd_vld  ;
wire [31:0] bus_fp_sch_data_out ;
wire        bus_me_rd_vld  ;
wire [31:0] bus_me_data_out ;

wire [31:0] bus_ins_cpt_data_in  ;
wire [16:0] bus_ins_cpt_addr_in  ;
wire [1:0]  bus_ins_cpt_addr_ctrl;

wire [31:0] bus_fp_sch_data_in   ;
wire [16:0] bus_fp_sch_addr_in   ;
wire [1:0]  bus_fp_sch_addr_ctrl ;

//reg [31:0]  np_data_out;
wire [ 15:0] capture_eth_type_00 ;
wire         capture_rdy_00      ;
wire [262:0] capture_data_o_00   ;
wire         capture_dval_00     ;
wire         capture_en_00       ;
wire [ 10:0] cpt_frame_len_00    ;
wire         capture_rdy_01      ; // 2022.5.1 xym
wire [255:0] capture_data_o_01   ; // 2022.5.1 xym
wire         capture_dval_01     ; // 2022.5.1 xym
wire         capture_en_01       ; // 2022.5.1 xym
wire [ 10:0] cpt_frame_len_01    ; // 2022.5.1 xym
wire         capture_rdy_02      ; // 2022.5.1 xym
wire [255:0] capture_data_o_02   ; // 2022.5.1 xym
wire         capture_dval_02     ; // 2022.5.1 xym
wire         capture_en_02       ; // 2022.5.1 xym
wire [ 10:0] cpt_frame_len_02    ; // 2022.5.1 xym
wire [  7:0] hm_id_00            ;
wire         cpt_busy_01         ; // 2022.5.1 xym

wire [2:0] pri_insert_00                ;
wire rx_rdy_insert_00                   ;
wire rx_ff_sop_insert_00                ;
wire rx_ff_eop_insert_00                ;
wire rx_ff_dval_insert_00               ;
wire rx_ff_dsav_insert_00               ;
wire [255:0] rx_ff_data_insert_00       ;
wire [4:0] rx_ff_mod_insert_00          ;
wire insert_empty_00                    ;
wire [7:0] insert_des_node_id_insert_00 ;

wire [255:0]  mac_data_o   ;
wire          mac_eop_o    ;
wire [4:0]    mac_mod_o    ;
wire          mac_sop_o    ;
wire          mac_dval_o   ;
wire          mac_dsav_o   ;

wire [255:0]  mac_data_i   ;
wire          mac_eop_i    ;
wire [4:0]    mac_mod_i    ;
wire          mac_sop_i_40_0    ;
wire          mac_dval_i   ;

wire [255:0]pkt_data_o ;
wire pkt_eop_o  ;
wire [4:0]pkt_mod_o  ;
wire pkt_sop_o  ;
wire pkt_dval_o ;
wire pkt_dsav_o ;

reg  bus_mac_rx2tx_loop_en_temp;
reg  bus_mac_rx2tx_loop_en     ;

reg  phy_ctrl_register_16_ff ;

//---------------------------------------------------------------
//dma channel sel , 2022.5.1 xym
//---------------------------------------------------------------
reg        bus_axi_ttvalid ;
reg        bus_axi_ttlast  ;
reg [ 7:0] bus_axi_ttkeep  ;
reg [63:0] bus_axi_ttdata  ;
// reg  [ 6:0] bus0_axi_ttuser ;
wire       bus_axi_ttready ;

wire        bus_axi_rtvalid ;
wire        bus_axi_rtlast  ;
wire [ 7:0] bus_axi_rtkeep  ;
wire [63:0] bus_axi_rtdata  ;
wire [89:0] bus_axi_rtuser  ;
reg         bus_axi_rtready ;

wire        np_bus_axi_ttvalid ;
wire        np_bus_axi_ttlast  ;
wire [ 7:0] np_bus_axi_ttkeep  ;
wire [63:0] np_bus_axi_ttdata  ;
reg         np_bus_axi_ttready ;

reg         np_bus_axi_rtvalid ;
reg         np_bus_axi_rtlast  ;
reg  [ 7:0] np_bus_axi_rtkeep  ;
reg  [63:0] np_bus_axi_rtdata  ;
wire        np_bus_axi_rtready ;

//40MAC_ll_0 -- crossbar_out

reg [31:0]np_data_in_d1,np_data_in_d2;
reg         np_wr               ;
reg         np_rd               ;
reg         np_sel_en           ;

reg         [31:0]ahb_cfg_rd_data_i;
wire        [31:0]ahb_cfg_addr_o;
wire        [31:0]ahb_cfg_wr_data_o;
wire        ahb_cfg_wr_en_o;
wire        ahb_cfg_rd_en_o;

wire        phy_rd_data_vld;
wire [31:0] phy_rd_data;
wire        cr_para_clk;
wire [15:0] cr_para_addr;
wire        cr_para_sel;
wire        cr_para_wr_en;
wire        cr_para_rd_en;
wire [15:0] cr_para_wr_data;

wire [15:0] cr_para_rd_data;
wire        cr_para_ack;


//原mac 100 top
(*mark_debug = "true"*) reg  [31:0]   pkt_in_cnt;
(*mark_debug = "true"*) reg  [31:0]   pkt_cbo_cnt;

// DFT port
wire sync_mac_reset_reg25 ; //high active
hdfwd_rstp_sync i_sync_mac_reset_reg25 ( sync_mac_reset_reg25, ff_clk, reset_register[25], ~pkt_rstn, testmode, 1'b0 );

always@(cluster_id) begin
  case(cluster_id)
    2'b00: src_node_id = 8'b0000_0001 ;
    2'b01: src_node_id = 8'b0000_0010 ;
    2'b10: src_node_id = 8'b0000_0100 ;
    2'b11: src_node_id = 8'b0000_1000 ;
  endcase
end

 eth_mac_phy U_eth_mac_phy_0(
 `ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
   .rx0_cdr_ppm_max   ( 5'd18 ),//input  [4:0]
   .rx0_ppm_drift     (  ),//output [5:0]
   .rx0_ppm_drift_vld (  ),//output
   .rx1_cdr_ppm_max   ( 5'd18 ),//input  [4:0]
   .rx1_ppm_drift     (  ),//output [5:0]
   .rx1_ppm_drift_vld (  ),//output
   .rx2_cdr_ppm_max   ( 5'd18 ),//input  [4:0]
   .rx2_ppm_drift     (  ),//output [5:0]
   .rx2_ppm_drift_vld (  ),//output
   .rx3_cdr_ppm_max   ( 5'd18 ),//input  [4:0]
   .rx3_ppm_drift     (  ),//output [5:0]
   .rx3_ppm_drift_vld (  ),//output
 `endif
  //vss&vdd
 `ifdef DWC_E12MP_X4NS_PG_PINS
   .vp               (vp              ),
 `endif
 `ifdef DWC_E12MP_X4NS_PG_PINS
 `ifdef DWC_PMA_PADS_PWRSW
 `else
   .vpdig            (vpdig          ),
 `endif
 `endif
 `ifdef DWC_E12MP_X4NS_PG_PINS
   .vph              (vph             ),
 `endif
 `ifdef DWC_E12MP_X4NS_PG_PINS
 `ifdef DWC_PMA_PADS_PWRSW
 `else
   .vptx0            (vptx0            ),
 `endif
 `endif
 `ifdef DWC_E12MP_X4NS_PG_PINS
 `ifdef DWC_PMA_PADS_PWRSW
 `else
   .vptx1            (vptx1            ),
 `endif
 `endif
 `ifdef DWC_E12MP_X4NS_PG_PINS
 `ifdef DWC_PMA_PADS_PWRSW
 `else
   .vptx2            (vptx2            ),
 `endif
 `endif
 `ifdef DWC_E12MP_X4NS_PG_PINS
 `ifdef DWC_PMA_PADS_PWRSW
 `else
   .vptx3            (vptx3            ),
 `endif
 `endif
 `ifdef DWC_E12MP_X4NS_PG_PINS
   .vsscore_0        (vsscore_0       ),
 `endif
 `ifdef DWC_E12MP_X4NS_PG_PINS
   .vsscore_1        (vsscore_1       ),
 `endif
 `ifdef DWC_E12MP_X4NS_PG_PINS
   .vsscore_2        (vsscore_2       ),
 `endif
 `ifdef DWC_PMA_PADS_PWRSW
   .ana_pwr_en       (                 ),
 `endif
 `ifdef DWC_PMA_PADS_PWRSW
   .ana_pwr_stable   (                 ),
 `endif
 `ifdef DWC_E12MP_X4NS_PG_PINS
   .gd               (gd               ),
 `endif

//Boundary Scan Signals
   .atb_f_p          (                 ),//leave unconnected when integrating the PHY
   .atb_s_m          (                 ),//leave unconnected when integrating the PHY
   .atb_s_p          (                 ),//leave unconnected when integrating the PHY
   .bs_acmode        (1'd0             ),//1'd0
   .bs_actest        (1'd0             ),
   .bs_cdr           (1'd1             ),//1'd1
   .bs_ce            (1'd0             ),//1'd0
   .bs_rx_bigswing   (1'b1             ),
   .bs_rx_init       (1'd0             ),//1'd0
   .bs_rx_level      (5'd9             ),//5'd9
   .bs_sdr           (1'b0             ),
   .bs_tdi           (1'b0             ),
   .bs_tdo           (                 ),
   .bs_tx_lowswing   (1'b0             ),
   .bs_udr           (1'b0             ),

 //   cr_signals
   .cr_para_ack      (cr_para_ack      ),//(                 ),
   .cr_para_addr     (cr_para_addr     ),//(16'b0            ),
   .cr_para_clk      (cr_para_clk      ),//(1'b0             ), //1'd0
   .cr_para_rd_data  (cr_para_rd_data  ),//(                 ),
   .cr_para_rd_en    (cr_para_rd_en    ),//(1'b0             ),
   .cr_para_sel      (cr_para_sel      ),//(1'b0             ),
   .cr_para_wr_data  (cr_para_wr_data  ),//(16'b0            ),
   .cr_para_wr_en    (cr_para_wr_en    ),//(1'b0             ),
   .dtb_out          (                 ),//(                 ),

     //jtag signals
   .jtag_tck         (jtag_tck         ),//1'd0
   .jtag_tdi         (jtag_tdi         ),//1'd0
   .jtag_tdo         (jtag_tdo         ),
   .jtag_tdo_en      (jtag_tdo_en      ),
   .jtag_tms         (jtag_tms         ),
   .jtag_trst_n      (jtag_trst_n      ),

   //PG Signals
   .pcs_pwr_stable   (phy_ctrl_register[9]   ),//1'd1
   .pg_mode_en       (phy_ctrl_register[8]   ),//1'd0
   .pg_reset         (reset_register[8]      ),//1'd0
   .pma_pwr_stable   (phy_ctrl_register[7]   ),//1'd1
   .pcs_pwr_en       (                       ),
   .pma_pwr_en       (                       ),
 
     //Loopback Signals
   .lanex_rx2tx_par_lb_en(phy_ctrl_register[3]),
   .lanex_tx2rx_ser_lb_en(phy_ctrl_register[2]),

   //clk and clk_en
   .ref_pad_clk_m    (ref_pad_clk_m        ),
   .ref_pad_clk_p    (ref_pad_clk_p        ),
   .ref_repeat_clk_en(phy_ctrl_register[4] ),
   .ref_repeat_clk_m (clk_repeat_clk_m     ),
   .ref_repeat_clk_p (clk_repeat_clk_p     ),
   .phy_ref_dig_clk  (phy_ref_dig_clk      ),
   .phy_reset        (reset_register[9]    ),
   .ref_clk_en       (phy_ctrl_register[6] ),
   .ref_use_pad      (phy_ctrl_register[5] ),

   .ref_alt_clk_m    (ref_alt_clk_m       ),
   .ref_alt_clk_p    (ref_alt_clk_p       ),
   .ref_clk_req      (                    ),
   .rtune_req        (req_lb_register[8]  ),
   .rtune_ack        (ack_register_temp[8]),

   //Resistor Tune Signals
   .resref           (resref             ), //inout
   
   //serial data signals
   .res_ack_in       (res_ack_in       ),//phy交互
   .res_ack_out      (res_ack_out      ),
   .res_req_in       (res_req_in       ),
   .res_req_out      (res_req_out      ),
 
   .rx0_req          (req_lb_register[0]    ),
   .rx0_ack          (ack_register_temp[0]  ),
   .rx1_req          (req_lb_register[1]    ),
   .rx1_ack          (ack_register_temp[1]  ),
   .rx2_req          (req_lb_register[2]    ),
   .rx2_ack          (ack_register_temp[2]  ),
   .rx3_req          (req_lb_register[3]    ),
   .rx3_ack          (ack_register_temp[3]  ),
 
   .rx0_m            (rx0_m                  ),
   .rx0_p            (rx0_p                  ),
   .rx0_reset        (reset_register[0]      ),
 
   .rx1_m            (rx1_m                  ),
   .rx1_p            (rx1_p                  ),
   .rx1_reset        (reset_register[1]      ),
 
   .rx2_m            (rx2_m                  ),
   .rx2_p            (rx2_p                  ),
   .rx2_reset        (reset_register[2]      ),
 
   .rx3_m            (rx3_m                  ),
   .rx3_p            (rx3_p                  ),
   .rx3_reset        (reset_register[3]      ),

   .scan_cr_clk             (phy_scan_clk    ),// DFT port
   .scan_cr_in              (132'd0   ),
   .scan_cr_out             (         ),
   .scan_mode               (testmode ),// DFT port
   .scan_mplla_div16p5_clk  (1'd0     ),
   .scan_mplla_div16p5_in   (1'd0     ),
   .scan_mplla_div16p5_out  (         ),
   .scan_mplla_div33_clk    (1'd0     ),
   .scan_mplla_div66_clk    (1'd0     ),
   .scan_mplla_div_clk      (1'd0     ),
   .scan_mplla_div_in       (1'd0     ),
   .scan_mplla_div_out      (         ),
   .scan_mplla_dword_clk    (1'd0     ),
   .scan_mplla_dword_in     (1'd0     ),
   .scan_mplla_dword_out    (         ),
   .scan_mplla_fb_clk       (1'd0     ),
   .scan_mplla_fb_in        (1'd0     ),
   .scan_mplla_fb_out       (         ),
   .scan_mplla_oword_clk    (1'd0     ),
   .scan_mplla_qword_clk    (1'd0     ),
   .scan_mplla_qword_in     (1'd0     ),
   .scan_mplla_qword_out    (         ),
   .scan_mplla_ref_clk      (1'd0     ),
   .scan_mplla_ref_in       (1'd0     ),
   .scan_mplla_ref_out      (         ),
   .scan_mplla_ssc_clk      (1'd0     ),
   .scan_mplla_ssc_in       (2'd0     ),
   .scan_mplla_ssc_out      (         ),
   .scan_mplla_word_clk     (1'd0     ),
   .scan_mplla_word_in      (1'd0     ),
   .scan_mplla_word_out     (         ),
   .scan_mpllb_div_clk      (1'd0     ),
   .scan_mpllb_div_in       (1'd0     ),
   .scan_mpllb_div_out      (         ),
   .scan_mpllb_dword_clk    (1'd0     ),
   .scan_mpllb_dword_in     (1'd0     ),
   .scan_mpllb_dword_out    (         ),
   .scan_mpllb_fb_clk       (1'd0     ),
   .scan_mpllb_fb_in        (1'd0     ),
   .scan_mpllb_fb_out       (         ),
   .scan_mpllb_oword_clk    (1'd0     ),
   .scan_mpllb_qword_clk    (1'd0     ),
   .scan_mpllb_qword_in     (1'd0     ),
   .scan_mpllb_qword_out    (         ),
   .scan_mpllb_ref_clk      (1'd0     ),
   .scan_mpllb_ref_in       (1'd0     ),
   .scan_mpllb_ref_out      (         ),
   .scan_mpllb_ssc_clk      (1'd0     ),
   .scan_mpllb_ssc_in       (2'd0     ),
   .scan_mpllb_ssc_out      (         ),
   .scan_mpllb_word_clk     (1'd0     ),
   .scan_mpllb_word_in      (1'd0     ),
   .scan_mpllb_word_out     (         ),
   .scan_ref_clk            (1'd0     ),
   .scan_ref_in             (1'd0     ),
   .scan_ref_out            (         ),
   .scan_ref_dig_clk        (phy_scan_clk    ),// DFT port
   .scan_ref_dig_in         (10'd0    ),
   .scan_ref_dig_out        (         ),
   .scan_ref_range_clk      (1'd0     ),
   .scan_ref_range_in       (18'd0    ),
   .scan_ref_range_out      (         ),
   .scan_rx0_adpt_clk       (1'd0     ),
   .scan_rx0_adpt_in        (5'd0     ),
   .scan_rx0_adpt_out       (         ),
   .scan_rx0_asic_clk       (1'd0     ),
   .scan_rx0_asic_in        (1'd0     ),
   .scan_rx0_asic_out       (         ),
   .scan_rx0_div16p5_clk    (1'd0     ),
   .scan_rx0_div16p5_in     (1'd0     ),
   .scan_rx0_div16p5_out    (         ),
   .scan_rx0_dpll_clk       (1'd0     ),
   .scan_rx0_dpll_in        (1'd0     ),
   .scan_rx0_dpll_out       (         ),
   .scan_rx0_dword_clk      (1'd0     ),
   .scan_rx0_dword_in       (9'd0     ),
   .scan_rx0_dword_out      (         ),
   .scan_rx0_scope_clk      (1'd0     ),
   .scan_rx0_scope_in       (1'd0     ),
   .scan_rx0_scope_out      (         ),
   .scan_rx0_stat_clk       (1'd0     ),
   .scan_rx0_stat_in        (7'd0     ),
   .scan_rx0_stat_out       (         ),
   .scan_rx0_word_clk       (1'd0     ),
   .scan_rx0_word_in        (1'd0     ),
   .scan_rx0_word_out       (         ),
   .scan_rx1_adpt_clk       (1'd0     ),
   .scan_rx1_adpt_in        (5'd0     ),
   .scan_rx1_adpt_out       (         ),
   .scan_rx1_asic_clk       (1'd0     ),
   .scan_rx1_asic_in        (1'd0     ),
   .scan_rx1_asic_out       (         ),
   .scan_rx1_div16p5_clk    (1'd0     ),
   .scan_rx1_div16p5_in     (1'd0     ),
   .scan_rx1_div16p5_out    (         ),
   .scan_rx1_dpll_clk       (1'd0     ),
   .scan_rx1_dpll_in        (1'd0     ),
   .scan_rx1_dpll_out       (         ),
   .scan_rx1_dword_clk      (1'd0     ),
   .scan_rx1_dword_in       (9'd0     ),
   .scan_rx1_dword_out      (         ),
   .scan_rx1_scope_clk      (1'd0     ),
   .scan_rx1_scope_in       (1'd0     ),
   .scan_rx1_scope_out      (         ),
   .scan_rx1_stat_clk       (1'd0     ),
   .scan_rx1_stat_in        (7'd0     ),
   .scan_rx1_stat_out       (         ),
   .scan_rx1_word_clk       (1'd0     ),
   .scan_rx1_word_in        (1'd0     ),
   .scan_rx1_word_out       (         ),
   .scan_rx2_adpt_clk       (1'd0     ),
   .scan_rx2_adpt_in        (5'd0     ),
   .scan_rx2_adpt_out       (         ),
   .scan_rx2_asic_clk       (1'd0     ),
   .scan_rx2_asic_in        (1'd0     ),
   .scan_rx2_asic_out       (         ),
   .scan_rx2_div16p5_clk    (1'd0     ),
   .scan_rx2_div16p5_in     (1'd0     ),
   .scan_rx2_div16p5_out    (         ),
   .scan_rx2_dpll_clk       (1'd0     ),
   .scan_rx2_dpll_in        (1'd0     ),
   .scan_rx2_dpll_out       (         ),
   .scan_rx2_dword_clk      (1'd0     ),
   .scan_rx2_dword_in       (9'd0     ),
   .scan_rx2_dword_out      (         ),
   .scan_rx2_scope_clk      (1'd0     ),
   .scan_rx2_scope_in       (1'd0     ),
   .scan_rx2_scope_out      (         ),
   .scan_rx2_stat_clk       (1'd0     ),
   .scan_rx2_stat_in        (7'd0     ),
   .scan_rx2_stat_out       (         ),
   .scan_rx2_word_clk       (1'd0     ),
   .scan_rx2_word_in        (1'd0     ),
   .scan_rx2_word_out       (         ),
   .scan_rx3_adpt_clk       (1'd0     ),
   .scan_rx3_adpt_in        (5'd0     ),
   .scan_rx3_adpt_out       (         ),
   .scan_rx3_asic_clk       (1'd0     ),
   .scan_rx3_asic_in        (1'd0     ),
   .scan_rx3_asic_out       (         ),
   .scan_rx3_div16p5_clk    (1'd0     ),
   .scan_rx3_div16p5_in     (1'd0     ),
   .scan_rx3_div16p5_out    (         ),
   .scan_rx3_dpll_clk       (1'd0     ),
   .scan_rx3_dpll_in        (1'd0     ),
   .scan_rx3_dpll_out       (         ),
   .scan_rx3_dword_clk      (1'd0     ),
   .scan_rx3_dword_in       (9'd0     ),
   .scan_rx3_dword_out      (         ),
   .scan_rx3_scope_clk      (1'd0     ),
   .scan_rx3_scope_in       (1'd0     ),
   .scan_rx3_scope_out      (         ),
   .scan_rx3_stat_clk       (1'd0     ),
   .scan_rx3_stat_in        (7'd0     ),
   .scan_rx3_stat_out       (         ),
   .scan_rx3_word_clk       (1'd0     ),
   .scan_rx3_word_in        (1'd0     ),
   .scan_rx3_word_out       (         ),
   .scan_set_rst            (~pkt_rstn       ),// DFT port
   .scan_shift              (se       ),// DFT port
   .scan_shift_cg           (se       ),// DFT port
   .scan_tx0_ana_dword_clk  (1'd0     ),
   .scan_tx0_ana_dword_in   (1'd0     ),
   .scan_tx0_ana_dword_out  (         ),
   .scan_tx0_ana_word_clk   (1'd0     ),
   .scan_tx0_ana_word_in    (1'd0     ),
   .scan_tx0_ana_word_out   (         ),
   .scan_tx0_asic_dword_clk (1'd0     ),
   .scan_tx0_asic_dword_in  (1'd0     ),
   .scan_tx0_asic_dword_out (         ),
   .scan_tx0_in             (2'd0     ),
   .scan_tx0_out            (         ),
   .scan_tx1_ana_dword_clk  (1'd0     ),
   .scan_tx1_ana_dword_in   (1'd0     ),
   .scan_tx1_ana_dword_out  (         ),
   .scan_tx1_ana_word_clk   (1'd0     ),
   .scan_tx1_ana_word_in    (1'd0     ),
   .scan_tx1_ana_word_out   (         ),
   .scan_tx1_asic_dword_clk (1'd0     ),
   .scan_tx1_asic_dword_in  (1'd0     ),
   .scan_tx1_asic_dword_out (         ),
   .scan_tx1_in             (2'd0     ),
   .scan_tx1_out            (         ),
   .scan_tx2_ana_dword_clk  (1'd0     ),
   .scan_tx2_ana_dword_in   (1'd0     ),
   .scan_tx2_ana_dword_out  (         ),
   .scan_tx2_ana_word_clk   (1'd0     ),
   .scan_tx2_ana_word_in    (1'd0     ),
   .scan_tx2_ana_word_out   (         ),
   .scan_tx2_asic_dword_clk (1'd0     ),
   .scan_tx2_asic_dword_in  (1'd0     ),
   .scan_tx2_asic_dword_out (         ),
   .scan_tx2_in             (2'd0     ),
   .scan_tx2_out            (         ),
   .scan_tx3_ana_dword_clk  (1'd0     ),
   .scan_tx3_ana_dword_in   (1'd0     ),
   .scan_tx3_ana_dword_out  (         ),
   .scan_tx3_ana_word_clk   (1'd0     ),
   .scan_tx3_ana_word_in    (1'd0     ),
   .scan_tx3_ana_word_out   (         ),
   .scan_tx3_asic_dword_clk (1'd0     ),
   .scan_tx3_asic_dword_in  (1'd0     ),
   .scan_tx3_asic_dword_out (         ),
   .scan_tx3_in             (2'd0     ),
   .scan_tx3_out            (         ),    
   .test_burnin             (phy_ctrl_register[11] ),//1'd1
   .test_powerdown          (phy_ctrl_register[10] ),//1'd0
 
   .tx0_req                  (req_lb_register[4]         ),
   .tx0_ack                  (ack_register_temp[4]       ),
   .tx1_req                  (req_lb_register[5]         ),
   .tx1_ack                  (ack_register_temp[5]       ),
   .tx2_req                  (req_lb_register[6]         ),
   .tx2_ack                  (ack_register_temp[6]       ),
   .tx3_req                  (req_lb_register[7]         ),
   .tx3_ack                  (ack_register_temp[7]       ),
 
   .tx0_m                    (tx0_m                      ),
   .tx0_p                    (tx0_p                      ),
   .tx0_reset                (reset_register[4]          ),
 
   .tx1_m                    (tx1_m                      ),
   .tx1_p                    (tx1_p                      ),
   .tx1_reset                (reset_register[5]          ),
 
   .tx2_m                    (tx2_m                      ),
   .tx2_p                    (tx2_p                      ),
   .tx2_reset                (reset_register[6]          ),
 
   .tx3_m                    (tx3_m                      ),
   .tx3_p                    (tx3_p                      ),
   .tx3_reset                (reset_register[7]          ),
   .lane_40Geth_ena          (phy_ctrl_register[0]       ),

 //mac signals
 .ref_ff_clk_630plus       (ref_ff_clk_630plus         ),
 .ref_clk                  (ref_clk                    ),
 .ff_clk                   (ff_clk                     ),
 .reg_clk                  (reg_clk                    ),
 .clk_rdy                  (                           ),
 .sd_tx2rx_par_lb_en       (phy_ctrl_register[1]       ),
 //reset
 .mac_reset                (sync_mac_reset_reg25       ),// DFT port
 // .mac_reset                (reset_register[25]         ),
 .reset_reg_clk            (reset_register[10]         ),
 .mac_reset_ref_clk        (reset_register[11]         ),
 .mac_reset_ff_rx_clk      (reset_register[13]         ),
 .mac_reset_ff_tx_clk      (reset_register[12]         ),
 .xlaui_reset_rx_clk       (reset_register[24:21]      ),
 .xlaui_reset_tx_clk       (reset_register[20]         ),
 .xlaui_reset_ref_clk      (reset_register[19]         ),
 .xaui_reset_rx_clk        (reset_register[18:15]      ),
 .xaui_reset_tx_clk        (reset_register[14]         ),
 // AXI Interface
 // -------------
 
   // TX Application interface
   // ------------------------
   .axi_ttvalid(bus_axi_ttvalid ),                      //  tVALID -> valid transaction
   .axi_ttlast (bus_axi_ttlast  ),                      //  tVALID -> last transaction for a frame
   .axi_ttkeep (bus_axi_ttkeep  ),                      //  tKEEP  -> valid byte qualifier(), 1 bit per byte in tdata
   .axi_ttdata (bus_axi_ttdata  ),                      //  tDATA  -> frame data(), left aligned
   .axi_ttuser (7'h20           ),                      //  tUSER  -> sideband data. 
   .axi_ttready(bus_axi_ttready ),                      //  tREADY -> interface backpressure
   // RX Application interface
   // ------------------------
   .axi_rtvalid(bus_axi_rtvalid ),                      //  tVALID -> valid transaction
   .axi_rtlast (bus_axi_rtlast  ),                      //  tVALID -> last transaction for a frame
   .axi_rtkeep (bus_axi_rtkeep  ),                      //  tKEEP  -> valid byte qualifier(), 1 bit per byte in tdata
   .axi_rtdata (bus_axi_rtdata  ),                      //  tDATA  -> frame data(), left aligned
   .axi_rtuser (bus_axi_rtuser  ),                      //  tUSER  -> sideband data. 
   .axi_rtready(bus_axi_rtready ),                      //  tREADY -> interface backpressure
 
 //  ------------------- //
 //  Register Interfaces //
 //  ------------------- //
 
   //  10Geth PCS
   //  ----------
   
   .xpcs_reg_wren(xpcs_reg_wren ),                   //  Write Enable  
   .xpcs_reg_rden(xpcs_reg_rden ),                   //  Read Enable  
   .xpcs_reg_addr(xpcs_reg_addr ),                   //  Register Address
   .xpcs_reg_din (xpcs_reg_din  ),                   //  Write Data  
   .xpcs_reg_dout(xpcs_reg_dout ),                   //  Read Data  
   .xpcs_reg_busy(xpcs_reg_busy ),                   //  Interface Busy  
 
   //  40Geth PCS
   //  ----------
   
   .xlpcs_reg_wren(xlpcs_reg_wren ),                 //  Write Enable  
   .xlpcs_reg_rden(xlpcs_reg_rden ),                 //  Read Enable  
   .xlpcs_reg_addr(xlpcs_reg_addr ),                 //  Register Address
   .xlpcs_reg_din (xlpcs_reg_din  ),                 //  Write Data  
   .xlpcs_reg_dout(xlpcs_reg_dout ),                 //  Read Data  
   .xlpcs_reg_busy(xlpcs_reg_busy ),                 //  Interface Busy 
 
   //  MAC
   //  -----
   .mac_reg_wren(mac_reg_wren ),                     //  Write Enable    
   .mac_reg_rden(mac_reg_rden ),                     //  Read Enable     
   .mac_reg_addr(mac_reg_addr ),                     //  Register Address
   .mac_reg_din (mac_reg_din  ),                     //  Write Data      
   .mac_reg_dout(mac_reg_dout ),                     //  Read Data       
   .mac_reg_busy(mac_reg_busy ),                     //  Interface Busy  
   .mac_reg_lowp_ena(mac_reg_lowp_ena ),             //  Low Power Generation
   // .rf_2p_cfg_register(rf_2p_cfg_register),
   // .ram_dp_cfg_register(ram_dp_cfg_register),
 // XAUI PCS Status
 // ---------------
   .x_align_done (mac_pcs_status_register0_temp[20]    ),                 //  Lane Alignment Done
   .x_disp_err   (mac_pcs_status_register0_temp[19:16] ),                 //  Disparity Error Indication
   .x_char_err   (mac_pcs_status_register0_temp[15:12] ),                 //  Character Error Indication
   .x_sync       (mac_pcs_status_register0_temp[11:8]  ),                 //  Channel Synchronization Indication
   .x_cg_align   (mac_pcs_status_register0_temp[7:4]   ),                 //  Code Group Alignment Indication
   .x_pat        (mac_pcs_status_register0_temp[3:0]   ),                 //  Comma Detected Indication
 
 // XLAUI PCS Status
 // ----------------
   .xl_ber_timer_done(mac_pcs_status_register0_temp[27]    ),                //  Hi BER measure window
   .xl_block_lock    (mac_pcs_status_register0_temp[26:23] ),                //  Block lock state reached
   .xl_align_done    (mac_pcs_status_register0_temp[22]    ),                //  Alignment marker lock state reached
   .xl_hi_ber        (mac_pcs_status_register0_temp[21]    ),                //  High Bit Error
 
   //  Configuration
   //  -------------
   .pcs_40Geth_ena   (phy_ctrl_register[12]   ),                //  Enable 40Geth operation
 
 //  ------------------------- //
 //  100Geth PCS Mode Settings //
 //  ------------------------- //
 
   //  MAC
   //  -----
   .mac_lpi_txhold   (mac_pcs_status_register1[11]       ),                 //  Transmit Hold Command
   .mac_tx_loc_fault (mac_pcs_status_register1[10]       ),                 //  Force RS TX to send LF sequences
   .mac_tx_rem_fault (mac_pcs_status_register1[9]        ),                 //  Force RS TX to send RF sequences
   .mac_tx_li_fault  (mac_pcs_status_register1[8]        ),                 //  Transmit Link Interruption Command
   .mac_loc_fault    (mac_pcs_status_register2_temp[16]  ),                 //  RX receives LF sequences
   .mac_rem_fault    (mac_pcs_status_register2_temp[15]  ),                 //  RX receives RF sequences
   .mac_li_fault     (mac_pcs_status_register2_temp[14]  ),                 //  Receive Link Interruption
 
   .mac_tx_ts_val    (mac_pcs_status_register2_temp[13]      ),                  //  Frame transmitted
   .mac_tx_ts_id     (mac_pcs_status_register2_temp[12:9]    ),                  //  ID of frame
   .mac_tx_ts        (mac_tx_ts          ),                  //  Timestamp
   .mac_frc_in_tx    (mac_frc_in_tx      ),                  //  Timestamp Timer (nanoseconds)
   .mac_frc_in_rx    (mac_frc_in_rx      ),                  //  Timestamp Timer (nanoseconds)
   .mac_pfc_mode     (mac_pcs_status_register2_temp[8]       ),                  //  PFC Mode Indication
   .mac_pause_on     (mac_pcs_status_register2_temp[7:0]     ),                  //  Transmit Paused/Class Congestion Indication
   .mac_xoff_gen     (mac_pcs_status_register1[7:0]          )                   //  Transmit Flow Control Command
 );


    MAC2NP_TOP MAC2NP_TOP_0(
        .rx_core_clk    ( ff_clk  ),
        .user_rx_resetn ( ~sync_mac_reset_reg25 ),// DFT port

        .ram_2p_cfg_register(ram_2p_cfg_register ),
        .ram_dp_cfg_register(ram_dp_cfg_register ),

        .rx_axis_tvalid   (np_bus_axi_rtvalid ),// 2022.5.1 xym
        .rx_axis_tdata    (np_bus_axi_rtdata  ),// 2022.5.1 xym
        .rx_axis_tlast    (np_bus_axi_rtlast  ),// 2022.5.1 xym
        .rx_axis_tkeep    (np_bus_axi_rtkeep  ),// 2022.5.1 xym
        .rx_axis_tready   (np_bus_axi_rtready ),// 2022.5.1 xym

        .tx_axis_tvalid   (np_bus_axi_ttvalid ),// 2022.5.1 xym
        .tx_axis_tdata    (np_bus_axi_ttdata  ),// 2022.5.1 xym
        .tx_axis_tlast    (np_bus_axi_ttlast  ),// 2022.5.1 xym
        .tx_axis_tkeep    (np_bus_axi_ttkeep  ),// 2022.5.1 xym
        .tx_axis_tready   (np_bus_axi_ttready ),// 2022.5.1 xym

        // .rx_axis_tvalid   (bus_axi_rtvalid ),
        // .rx_axis_tdata    (bus_axi_rtdata  ),
        // .rx_axis_tlast    (bus_axi_rtlast  ),
        // .rx_axis_tkeep    (bus_axi_rtkeep  ),
        // //.rx_axis_tuser    (bus_axi_rtuser  ),
        // .rx_axis_tready   (np_bus_axi_rtready ),

        // .tx_axis_tvalid   (np_bus_axi_ttvalid ),
        // .tx_axis_tdata    (np_bus_axi_ttdata  ),
        // .tx_axis_tlast    (np_bus_axi_ttlast  ),
        // .tx_axis_tkeep    (np_bus_axi_ttkeep  ),
        // //.tx_axis_tuser    (np_bus0_axi_ttuser  ),
        // .tx_axis_tready   (np_bus_axi_ttready ),

    `ifdef SIM
        .axi_valid_o    (bus_axi_valid_o ),
        .axi_data_o     (bus_axi_data_o  ),
        .axi_last_o     (bus_axi_last_o  ),
        .axi_keep_o     (bus_axi_keep_o  ),
        .axi_ready_o    (bus_axi_ready_o ),

        .axi_valid_i    (bus_axi_valid_i ),
        .axi_data_i     (bus_axi_data_i  ),
        .axi_last_i     (bus_axi_last_i  ),
        .axi_keep_i     (bus_axi_keep_i  ),
        .axi_ready_i    (bus_axi_ready_i ),
    `endif
    
        .pkt_clk          (pkt_clk    ),
        .pkt_rstn         (pkt_rstn   ),
        // .pkt_rstn         (~reset_register[25]     ),

        .pkt_rdy        (rx_rdy_mac  ),
        .pkt_data_o     (mac_data_o  ),
        .pkt_eop_o      (mac_eop_o   ),
        .pkt_mod_o      (mac_mod_o   ),
        .pkt_sop_o      (mac_sop_o   ),
        .pkt_dval_o     (mac_dval_o  ),
        .pkt_dsav_o     (mac_dsav_o  ),

        .pkt_data_i     (mac_data_i  ),
        .pkt_eop_i      (mac_eop_i   ),
        .pkt_mod_i      (mac_mod_i   ),
        // .pkt_sop_i      (mac_sop_i_40_0   ),
        .pkt_dval_i     (mac_dval_i  ),
        .pkt_rdy_o      (emac_rx_ready   ),
        .testmode       (testmode    )// DFT port
    );

frame_test_gen #(
  // .frame_mac_dst(frame_mac_dst_bus),
  // .frame_mac_src(frame_mac_src_bus),
  .frame_length (frame_length_bus )
  )
U_frame_test_gen(
  .frame_mac_dst  (frame_mac_dst),
  .frame_mac_src  (frame_mac_src),

  .clk            (pkt_clk                    ),
  .rst_n          (pkt_rstn                   ),
  .frame_start    (phy_ctrl_register[13] ),//在外面和interface连 input [16:0]bus_phy_ctrl_register
  .frame_rdy      (rx_rdy_mac                ),//和mac100top

  .pkt_test_sop   (pkt_test_sop             ),//wire pkt_test_sop
  .pkt_test_dvld  (pkt_test_dvld            ),//wire pkt_test_dvld
  .pkt_test_dsav  (pkt_test_dsav            ),//wire pkt_test_dsav
  .pkt_test_data  (pkt_test_data            ),//wire [255:0]pkt_test_data
  .pkt_test_eop   (pkt_test_eop             )// wire pkt_test_eop
  );

assign pkt_data_o = (phy_ctrl_register[14])?  pkt_test_data:mac_data_o;
assign pkt_eop_o  = (phy_ctrl_register[14])?  pkt_test_eop :mac_eop_o ;
assign pkt_mod_o  = (phy_ctrl_register[14])?  5'b0         :mac_mod_o ;
assign pkt_sop_o  = (phy_ctrl_register[14])?  pkt_test_sop :mac_sop_o ;
assign pkt_dval_o = (phy_ctrl_register[14])?  pkt_test_dvld:mac_dval_o;
assign pkt_dsav_o = (phy_ctrl_register[14])?  pkt_test_dsav:mac_dsav_o;

assign mac_data_i = (phy_ctrl_register[15])?  pkt_test_data:pkt_data_i;
assign mac_eop_i  = (phy_ctrl_register[15])?  pkt_test_eop :pkt_eop_i ;
assign mac_mod_i  = (phy_ctrl_register[15])?  5'b0         :pkt_mod_i ;
// assign mac_sop_i_40_0  = (bus_phy_ctrl_register[15])?  pkt_test_sop :pkt_sop_i_40_0 ;
assign mac_dval_i = (phy_ctrl_register[15])?  pkt_test_dvld:pkt_dval_i;

//---------------------------------------------------------------
//dma_channel_sel , 2022.5.1 xym
//dma_channel_sel protection , 2022.7.10 xym
//only to prevent metastable, not to guarantee function
//dma_channel_sel can only be changed during mac_reset asserting
//src: sel_cpu_scope pkt_clk
//dst: sel_mac_scope ff_clk
//dst: sel_np_scope  pkt_clk
//dst: sel_dma_scope axi_clk
//---------------------------------------------------------------
wire [1:0] sel_mac_scope ;
reg  [1:0] sel_np_scope  ;
// wire [1:0] sel_dma_scope ;

np_reg_sync #(.wid(2))
sel_sync_mac_scope(
  .d_clk(ff_clk),
  .rst_n(~sync_mac_reset_reg25),
  .din(dma_channel_sel),
  .dout(sel_mac_scope)
);

always @(posedge pkt_clk or negedge pkt_rstn) begin
  if(~pkt_rstn) begin
    sel_np_scope <= 2'b0;
  end else begin
    sel_np_scope <= dma_channel_sel;
  end
end

// np_reg_sync #(.wid(2))
// sel_sync_dma_scope(
//   .d_clk(m_axi_aclk_i),
//   .rst_n(m_axi_aresetn_i),
//   .din(dma_channel_sel),
//   .dout(sel_dma_scope)
// );

always @(*) begin
  if ( sel_mac_scope == 2'b10 ) begin // mode2 : mac - dma
    // mac scope
    bus_axi_ttvalid = dma_axi_ttvalid ;
    bus_axi_ttlast  = dma_axi_ttlast  ;
    bus_axi_ttkeep  = dma_axi_ttkeep  ;
    bus_axi_ttdata  = dma_axi_ttdata  ;
    bus_axi_rtready = dma_axi_rtready ;
  end
  else if ( sel_mac_scope == 2'b11 ) begin // mode3 : mac - np - dma
    // mac scope
    bus_axi_ttvalid = dma_axi_ttvalid    ;
    bus_axi_ttlast  = dma_axi_ttlast     ;
    bus_axi_ttkeep  = dma_axi_ttkeep     ;
    bus_axi_ttdata  = dma_axi_ttdata     ;
    bus_axi_rtready = np_bus_axi_rtready ;
  end
  else if ( bus_mac_rx2tx_loop_en == 1'b1 ) begin // mode1 + loop : 
    // mac scope
    bus_axi_ttvalid = bus_axi_rtvalid ;
    bus_axi_ttlast  = bus_axi_rtlast  ;
    bus_axi_ttkeep  = bus_axi_rtkeep  ;
    bus_axi_ttdata  = bus_axi_rtdata  ;
    bus_axi_rtready = bus_axi_ttready ;
  end
  else begin // default : mode1
    // mac scope
    bus_axi_ttvalid = np_bus_axi_ttvalid ;
    bus_axi_ttlast  = np_bus_axi_ttlast  ;
    bus_axi_ttkeep  = np_bus_axi_ttkeep  ;
    bus_axi_ttdata  = np_bus_axi_ttdata  ;
    bus_axi_rtready = np_bus_axi_rtready ;
  end
end

always @(*) begin
  if ( sel_np_scope == 2'b10 ) begin // mode2 : mac - dma
    // np scope
    np_bus_axi_rtvalid =  1'b0 ;
    np_bus_axi_rtlast  =  1'b0 ;
    np_bus_axi_rtkeep  =  8'd0 ;
    np_bus_axi_rtdata  = 64'd0 ;
    np_bus_axi_ttready =  1'b0 ;
  end
  else if ( sel_np_scope == 2'b11 ) begin // mode3 : mac - np - dma
    // np scope
    np_bus_axi_rtvalid = bus_axi_rtvalid ;
    np_bus_axi_rtlast  = bus_axi_rtlast  ;
    np_bus_axi_rtkeep  = bus_axi_rtkeep  ;
    np_bus_axi_rtdata  = bus_axi_rtdata  ;
    np_bus_axi_ttready = 1'b0 ;
  end
  else if ( phy_ctrl_register_16_ff == 1'b1 ) begin // mode1 + loop : 
    // np scope
    np_bus_axi_rtvalid =  1'b0 ;
    np_bus_axi_rtlast  =  1'b0 ;
    np_bus_axi_rtkeep  =  8'd0 ;
    np_bus_axi_rtdata  = 64'd0 ;
    np_bus_axi_ttready =  1'b0 ;
  end
  else begin // default : mode1
    // np scope
    np_bus_axi_rtvalid = bus_axi_rtvalid ;
    np_bus_axi_rtlast  = bus_axi_rtlast  ;
    np_bus_axi_rtkeep  = bus_axi_rtkeep  ;
    np_bus_axi_rtdata  = bus_axi_rtdata  ;
    np_bus_axi_ttready = bus_axi_ttready ;
  end
end

always @(*) begin
  if ( sel_dma_scope == 2'b10 ) begin // mode2 : mac - dma
    // dma scope
    dma_axi_rtvalid = bus_axi_rtvalid ;
    dma_axi_rtlast  = bus_axi_rtlast  ;
    dma_axi_rtkeep  = bus_axi_rtkeep  ;
    dma_axi_rtdata  = bus_axi_rtdata  ;
    dma_axi_ttready = bus_axi_ttready ;
  end
  else if ( sel_dma_scope == 2'b11 ) begin // mode3 : mac - np - dma
    // dma scope
    dma_axi_rtvalid =  1'b0 ;
    dma_axi_rtlast  =  1'b0 ;
    dma_axi_rtkeep  =  8'd0 ;
    dma_axi_rtdata  = 64'd0 ; // data is from capture_data_o_00 instead
    dma_axi_ttready = bus_axi_ttready ;
  end
  // else if ( bus_mac_rx2tx_loop_en == 1'b1 ) begin // mode1 + loop : 
  //   // dma scope
  //   dma_axi_rtvalid =  1'b0 ;
  //   dma_axi_rtlast  =  1'b0 ;
  //   dma_axi_rtkeep  =  8'd0 ;
  //   dma_axi_rtdata  = 64'd0 ;
  //   dma_axi_ttready =  1'b0 ;
  // end
  else begin // default : mode1
    // dma scope
    dma_axi_rtvalid =  1'b0 ;
    dma_axi_rtlast  =  1'b0 ;
    dma_axi_rtkeep  =  8'd0 ;
    dma_axi_rtdata  = 64'd0 ;
    dma_axi_ttready =  1'b0 ;
  end
end

// assign bus_axi_ttvalid     = (bus_mac_rx2tx_loop_en)? bus_axi_rtvalid:np_bus_axi_ttvalid;
// assign bus_axi_ttlast      = (bus_mac_rx2tx_loop_en)? bus_axi_rtlast :np_bus_axi_ttlast ;
// assign bus_axi_ttkeep      = (bus_mac_rx2tx_loop_en)? bus_axi_rtkeep :np_bus_axi_ttkeep ;
// assign bus_axi_ttdata      = (bus_mac_rx2tx_loop_en)? bus_axi_rtdata :np_bus_axi_ttdata ;
// assign np_bus_axi_ttready  = (bus_mac_rx2tx_loop_en)? 1'b0           :bus_axi_ttready;
// assign bus_axi_rtready     = (bus_mac_rx2tx_loop_en)? bus_axi_ttready:np_bus_axi_rtready;

always @(posedge ff_clk) begin
    bus_mac_rx2tx_loop_en_temp   <=  phy_ctrl_register[16];
    bus_mac_rx2tx_loop_en        <=  bus_mac_rx2tx_loop_en_temp;
end

always @(posedge pkt_clk or negedge pkt_rstn) begin
  if(~pkt_rstn) begin
    phy_ctrl_register_16_ff <= 1'b0;
  end else begin
    phy_ctrl_register_16_ff <= phy_ctrl_register[16];
  end
end

fp_and_sch_top inst_fp_and_sch_top_0
  (
    .clk                             (pkt_clk),
    .rst_n                           (pkt_rstn),
    .fp_sch_init_done                (fp_sch_init_done),
    .ram_dp_cfg_register             (ram_dp_cfg_register),
    .ram_2p_cfg_register             (ram_2p_cfg_register),
    .rf_2p_cfg_register              (rf_2p_cfg_register) ,
    //with CPU config
    //ME1-ME6
    .np_cpu_wr_data(bus_fp_sch_data_in),
    .np_cpu_addr   (bus_fp_sch_addr_in),
    .np_cpu_ram_ctr(bus_fp_sch_addr_ctrl),
    .np_cpu_rd_data(bus_fp_sch_data_out),
    `ifndef NO_CPU_MODE
    .fp_sch_rd_vld (bus_fp_sch_rd_vld),
    `else
    //\u914d\u7f6e\u5355\u64ad\u8f6c\u53d1\u8868
    .CPU_unicam_addr                 (CPU_unicam_addr /*bus1_me_array_unicam7_dpram_addr  */),
    .CPU_unicam_dout                 (CPU_unicam_dout /*bus1_me_array_unicam7_dpram_rdata */),
    .CPU_unicam_wren                 (CPU_unicam_wren /*bus1_me_array_unicam7_dpram_wen   */),
    .CPU_unicam_din                  (CPU_unicam_din  /*bus1_me_array_unicam7_dpram_wdata */),
    .CPU_unicam_live_val             (1'b1/*CPU_unicam_live_val*/),
    .CPU_unicam_live_time            (32'b0/*CPU_unicam_live_time*/),
     //\u914d\u7f6e\u7ec4\u64ad\u8f6c\u53d1\u8868
    .CPU_mulcam_wren                 (1'b0/*CPU_mulcam_wren*/),
    .CPU_mulcam_modify               (32'b0/*CPU_mulcam_modify*/),
    .CPU_mulcam_group_mac            (32'b0/*CPU_mulcam_group_mac*/),
    .CPU_mulcam_member               (32'b0/*CPU_mulcam_member*/),
    .CPU_mulcam_rden                 (1'b0/*CPU_mulcam_rden*/),
    .CPU_mulcam_addr                 (12'b0/*CPU_mulcam_addr*/),
    .CPU_mulcam_dout                 (CPU_mulcam_dout),
    //\u914d\u7f6eDWRR\u8c03\u5ea6\u4ee5\u53ca\u6743\u91cd
    .DWRR_en                         (1'b0 /*bus1_rw_reg_dwrr_en     */),
    .WEIGHT7                         (16'd0/*bus1_rw_reg_dwrr_weight7*/),
    .WEIGHT6                         (16'd0/*bus1_rw_reg_dwrr_weight6*/),
    .WEIGHT5                         (16'd0/*bus1_rw_reg_dwrr_weight5*/),
    .WEIGHT4                         (16'd0/*bus1_rw_reg_dwrr_weight4*/),
    .WEIGHT3                         (16'd0/*bus1_rw_reg_dwrr_weight3*/),
    .WEIGHT2                         (16'd0/*bus1_rw_reg_dwrr_weight2*/),
    .WEIGHT1                         (16'd0/*bus1_rw_reg_dwrr_weight1*/),
    .WEIGHT0                         (16'd0/*bus1_rw_reg_dwrr_weight0*/),
    //\u914d\u7f6e\u961f\u5217\u8c03\u5ea6\u95e8
    .query_CPU_node_minmax_threshold (query_CPU_node_minmax_threshold_00                     ),
    .CPU_node_minmax_threshold_data  ({16'd192,16'd1024}/*CPU_node_minmax_threshold_data_00*/),
    .query_CPU_queue_max_threshold   (query_CPU_queue_max_threshold_00                       ),
    .CPU_queue_max_threshold_data    (32'd384/*CPU_queue_max_threshold_data_00*/             ),
    .CPU_BD_public_length            (32'd3304/*CPU_BD_public_length_00*/                    ),
    .query_CPU_node_min_threshold    (query_CPU_node_min_threshold_00                        ),
    .CPU_node_min_threshold_data     (32'd192/*CPU_node_min_threshold_data_00*/              ),
    `endif
    // .ro_reg_np_freeblocknumber_register    (bus1_ro_reg_np_freeblocknumber_register  ),
    // .ro_reg_np_mac_enqueue_cnt             (bus1_ro_reg_np_mac_enqueue_cnt           ),
    // .ro_reg_np_mac_enqueue_fail_cnt    (bus1_ro_reg_np_mac_enqueue_fail_cnt      ),
    // .ro_reg_np_enqueue_num                 (bus1_ro_reg_np_enqueue_num               ),
    // .ro_reg_np_dequeue_num                 (bus1_ro_reg_np_dequeue_num               ),
    // .ro_reg_np_max_rx_length               (bus1_ro_reg_np_max_rx_length             ),
    // .ro_reg_np_max_tx_length               (bus1_ro_reg_np_max_tx_length             ),
    // .rx_frame_cnt_node_0                  (bus1_rx_frame_cnt_node_0                 ),
    // .rx_frame_cnt_node_1                  (bus1_rx_frame_cnt_node_1                 ),
    // .rx_frame_cnt_node_2                  (bus1_rx_frame_cnt_node_2                 ),
    // .rx_frame_cnt_node_3                  (bus1_rx_frame_cnt_node_3                 ),
    // .rx_frame_cnt_node_4                  (bus1_rx_frame_cnt_node_4                 ),
    // .tx_frame_cnt_node_0                  (bus1_tx_frame_cnt_node_0                 ),
    // .tx_frame_cnt_node_1                  (bus1_tx_frame_cnt_node_1                 ),
    // .tx_frame_cnt_node_2                  (bus1_tx_frame_cnt_node_2                 ),
    // .tx_frame_cnt_node_3                  (bus1_tx_frame_cnt_node_3                 ),
    // .tx_frame_cnt_node_4                  (bus1_tx_frame_cnt_node_4                 ),
    //locallink\u683c\u5f0f\u6570\u636e\u5e27
    .pkt_sop                         (pkt_sop_o ),
    .pkt_eop                         (pkt_eop_o ),
    .pkt_dsav                        (pkt_dsav_o),
    .pkt_data                        (pkt_data_o),
    .pkt_dval                        (pkt_dval_o),
    .pkt_mod                         (pkt_mod_o ),
    // .src_node_id                     (8'b0000_0001/*src_node_id*/),
    .src_node_id                     (src_node_id/*src_node_id*/),
    .pkt_rdy                         (rx_rdy_mac),
    //\u56db\u8868\u540c\u6b65
    .bus1_table_addr2                (bus1_table_addr2             ),
    .bus1_table_ram_addr_convert     (bus1_table_ram_addr_convert ),
    .bus1_table_data2                (bus1_table_data2             ),
    .bus1_table_ram_data_convert     (bus1_table_ram_data_convert ),
    .bus1_table_wren2                (bus1_table_wren2             ),
    .bus1_table_ram_wr_en_convert    (bus1_table_ram_wr_en_convert),
    .bus2_table_addr2                (bus2_table_addr2             ),
    .bus2_table_ram_addr_convert     (bus2_table_ram_addr_convert ),
    .bus2_table_data2                (bus2_table_data2            ),
    .bus2_table_ram_data_convert     (bus2_table_ram_data_convert ),
    .bus2_table_wren2                (bus2_table_wren2             ),
    .bus2_table_ram_wr_en_convert    (bus2_table_ram_wr_en_convert),
    .bus3_table_addr2                (bus3_table_addr2             ),
    .bus3_table_ram_addr_convert     (bus3_table_ram_addr_convert ),
    .bus3_table_data2                (bus3_table_data2             ),
    .bus3_table_ram_data_convert     (bus3_table_ram_data_convert ),
    .bus3_table_wren2                (bus3_table_wren2             ),
    .bus3_table_ram_wr_en_convert    (bus3_table_ram_wr_en_convert),
    .bus4_table_addr2                (bus4_table_addr2             ),
    .bus4_table_ram_addr_convert     (bus4_table_ram_addr_convert ),
    .bus4_table_data2                (bus4_table_data2             ),
    .bus4_table_ram_data_convert     (bus4_table_ram_data_convert ),
    .bus4_table_wren2                (bus4_table_wren2             ),
    .bus4_table_ram_wr_en_convert    (bus4_table_ram_wr_en_convert), 
    //with insert
    .rx_rdy_insert                   (rx_rdy_insert_00),
    .rx_ff_sop_insert                (rx_ff_sop_insert_00),
    .rx_ff_eop_insert                (rx_ff_eop_insert_00),
    .rx_ff_dval_insert               (rx_ff_dval_insert_00),
    .rx_ff_dsav_insert               (rx_ff_dsav_insert_00),
    .rx_ff_data_insert               (rx_ff_data_insert_00),
    .rx_ff_mod_insert                (rx_ff_mod_insert_00),
    .insert_empty                    (insert_empty_00),
    .des_node_id_insert              (insert_des_node_id_insert_00),
    .pri_insert                      (pri_insert_00),
    //with capture
    .capture_eth_type                (16'h88b5/*capture_eth_type_00*/),
    .capture_rdy                     (capture_rdy_00),
    .capture_data_o                  (capture_data_o_00),
    .capture_dval                    (capture_dval_00),
    .capture_en                      (capture_en_00),
    .cpt_frame_len                   (cpt_frame_len_00),
    //with crossbar_ctrl_top
    .uni_tx_rdy0                     (uni_tx_rdy00),
    .uni_tx_rdy1                     (uni_tx_rdy01),
    .uni_tx_rdy2                     (uni_tx_rdy02),
    .uni_tx_rdy3                     (uni_tx_rdy03),
    .mul_tx_rdy0                     (mul_tx_rdy00),
    .mul_tx_rdy1                     (mul_tx_rdy01),
    .mul_tx_rdy2                     (mul_tx_rdy02),
    .mul_tx_rdy3                     (mul_tx_rdy03),
    .emac_data_in                    (emac_data_in          ),
    .emac_data_wren                  (emac_data_wren        ),
    .rx_address_dpram                (rx_address_dpram      ),
    .mac_dest_port_in                (mac_dest_port_in      ),
    .mul_indicate                    (mul_indicate          )
  );

  insert_capture_top U_insert_capture_top0(
    .rst_n                       (pkt_rstn                     ),
    .clk                         (pkt_clk                     ),
    .ram_2p_cfg_register         (ram_2p_cfg_register),
    // \u914d\u7f6e\u63a5\u53e3
    .np_data_out                 (bus_ins_cpt_data_out) ,
    .np_data_in                  (bus_ins_cpt_data_in) ,
    .np_addr_in                  (bus_ins_cpt_addr_in) ,
    .np_addr_ctrl                (bus_ins_cpt_addr_ctrl) ,
    .ins_cpt_rd_vld              (bus_ins_cpt_rd_vld) ,
    //\u6355\u83b7E\u53e3
    .cpt_em_data_val            (capture_dval_01             ),
    .cpt_em_data                (capture_data_o_01[255:0]    ),
    .em_cpt_en                  (capture_en_01               ),
    .em_hm_id                   (8'b0                        ),
    .em_cpt_frame_len           (cpt_frame_len_01            ),
    //\u6355\u83b7H\u53e3
    .cpt_hm_data_val            (1'b0                     ),
    .cpt_hm_data                (256'b0                   ),
    .hm_cpt_en                  (1'b0                     ),
    .hm_hm_id                   (8'b0                     ),
    .hm_cpt_frame_len           (11'd0                    ),
    .cpt_busy                   (cpt_busy_01              ),
     //\u63d2\u5165E\u53e3
    .pri_insert_e               (pri_insert_00               ),
    .insert_empty_e             (insert_empty_00             ),
    .rx_rdy_insert_e            (rx_rdy_insert_00            ),
    .insert_des_node_id_insert_e(insert_des_node_id_insert_00),
    .rx_ff_data_insert_e        (rx_ff_data_insert_00        ),
    .rx_ff_dval_insert_e        (rx_ff_dval_insert_00        ),
    .rx_ff_sop_insert_e         (rx_ff_sop_insert_00         ),
    .rx_ff_eop_insert_e         (rx_ff_eop_insert_00         ),
    .rx_ff_mod_insert_e         (rx_ff_mod_insert_00         ),
    .rx_ff_dsav_insert_e        (rx_ff_dsav_insert_00        ),
    //\u63d2\u5165H\u53e3
    .pri_insert_h               (                         ),
    .insert_empty_h             (                         ),
    .rx_rdy_insert_h            (1'b0                     ),
    .insert_des_node_id_insert_h(                         ),
    .rx_ff_data_insert_h        (                         ),
    .rx_ff_dval_insert_h        (                         ),
    .rx_ff_sop_insert_h         (                         ),
    .rx_ff_eop_insert_h         (                         ),
    .rx_ff_mod_insert_h         (                         ),
    .rx_ff_dsav_insert_h        (                         )
);

//原mac 100 top中的计数器
always @(posedge pkt_clk or negedge pkt_rstn) begin
  if (~pkt_rstn) begin
    pkt_in_cnt <= 32'b0;
  end
  else if (pkt_sop_o) begin
    pkt_in_cnt <= pkt_in_cnt + 32'b1;
  end
  else begin
    pkt_in_cnt <= pkt_in_cnt;
  end
end

always @(posedge pkt_clk or negedge pkt_rstn) begin
  if ( ~pkt_rstn) begin
    pkt_cbo_cnt <= 32'b0;
  end
  else if (pkt_sop_i) begin
    pkt_cbo_cnt <= pkt_cbo_cnt + 32'b1;
  end
  else begin
    pkt_cbo_cnt <= pkt_cbo_cnt;
  end
end

assign bus_ins_cpt_data_in   = np_data_in  ;
assign bus_ins_cpt_addr_in   = np_addr_in[16:0];
assign bus_ins_cpt_addr_ctrl = {np_wr_in,np_rd_in};

assign bus_fp_sch_data_in    = np_data_in  ;
assign bus_fp_sch_addr_in    = np_addr_in[16:0];
assign bus_fp_sch_addr_ctrl  = {np_wr_in,np_rd_in};

  always @(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn)
        np_data_out <= 32'b0;
    else if(bus_fp_sch_rd_vld)
        np_data_out <= bus_fp_sch_data_out;
    else if(bus_ins_cpt_rd_vld)
        np_data_out <= bus_ins_cpt_data_out;
    else if(bus_me_rd_vld)
        np_data_out <= bus_me_data_out;
    else if(phy_rd_data_vld)
        np_data_out <= phy_rd_data;
    else
        np_data_out <= np_data_out ;
  end

  always@(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn)
        bus_np_data_out_vld <= 1'b0;
    else if(bus_fp_sch_rd_vld || bus_ins_cpt_rd_vld || bus_me_rd_vld || phy_rd_data_vld)
        bus_np_data_out_vld <= 1'b1;
    else
        bus_np_data_out_vld <= 1'b0;
  end

  // scan_ME#(
  //      .CLUSTER_ID         ( CLUSTER_ID       )
  // )
  scan_ME u_scan_ME_Cluster0(
       .cluster_id         ( cluster_id      )
      ,.clk                ( pkt_clk         )
      ,.rst_n              ( pkt_rstn        )
      ,.np_rd_in           ( np_rd_in        )
      ,.np_addr_in         ( np_addr_in      )
      ,.np_data_out        ( bus_me_data_out )
      ,.np_data_out_vld    ( bus_me_rd_vld   )
  );

// 2022.5.1 xym
assign capture_dval_01   = ( sel_np_scope == 2'b11 ) ?   1'b0 : capture_dval_00   ;
assign capture_data_o_01 = ( sel_np_scope == 2'b11 ) ? 256'd0 : capture_data_o_00 ;
assign cpt_frame_len_01  = ( sel_np_scope == 2'b11 ) ?  11'd0 : cpt_frame_len_00  ;
assign capture_en_01     = ( sel_np_scope == 2'b11 ) ?   1'b0 : capture_en_00     ;

assign capture_dval_02   = ( sel_np_scope == 2'b11 ) ? capture_dval_00   :   1'b0 ;
assign capture_data_o_02 = ( sel_np_scope == 2'b11 ) ? capture_data_o_00 : 256'd0 ;
assign cpt_frame_len_02  = ( sel_np_scope == 2'b11 ) ? cpt_frame_len_00  :  11'd0 ;
assign capture_en_02     = ( sel_np_scope == 2'b11 ) ? capture_en_00     :   1'b0 ;

assign capture_rdy_01    = !cpt_busy_01 ;
assign capture_rdy_00    = ( sel_np_scope == 2'b11 ) ? capture_rdy_02 : capture_rdy_01 ;

ll2axi_fifo_dma_rx #(
    .DMA_DWIDTH (128) , // DMA Data Width
    .MEM_DWIDTH (256) , // MEM Data Width
    .MEM_AWIDTH (8  ) , // MEM Addr Width
    .LEN_DWIDTH (11 ) , // LEN Data Width
    .LEN_AWIDTH (6  )   // LEN Addr Width
  ) cpt2dma_channel (
    .wclk                ( pkt_clk ), // 312p5MHz PKT
    .rclk                ( dma_clk ), // 100MHz DMA
    .rstn_wclk           ( pkt_rstn ), // Low Active
    .rstn_rclk           ( dma_rstn ), // Low Active
    .ram_dp_cfg_register ( ram_dp_cfg_register ),
    // cap intf
    .capture_vld_i       ( capture_dval_02   ),
    .capture_data_i      ( capture_data_o_02 ),
    .capture_len_i       ( cpt_frame_len_02  ),
    .capture_en_i        ( capture_en_02     ),
    .capture_rdy_o       ( capture_rdy_02    ),
    // dma intf
    .rd_leng_en_i        ( dma_rd_leng_en_i  ),
    .rd_data_en_i        ( dma_rd_data_en_i  ),
    .rd_leng_vld_o       ( dma_rd_leng_vld_o ),
    .rd_dout_vld_o       ( dma_rd_dout_vld_o ),
    .rd_leng_o           ( dma_rd_leng_o     ),
    .rd_dout_o           ( dma_rd_dout_o     ),
    .empty_leng_o        ( dma_empty_o       ),
    .empty_data_o        ( dma_data_empty_o  )//5.23 xym
  );

bus_to_cr u_bus_to_cr(
  .hclk_i                  (hclk_i),
  .hresetn_i               (hresetn_i),
  .pkt_clk_i               (pkt_clk),
  .pkt_rstn_i              (pkt_rstn),
  .np_addr_i               (np_addr_in),
  .np_wr_i                 (np_wr_in),
  .np_wr_data_i            (np_data_in),
  .np_rd_i                 (np_rd_in),
  .np_rd_data_o            (phy_rd_data),
  .rd_data_vld_o           (phy_rd_data_vld),

  .testmode                (testmode),

  .cr_para_clk_o           (cr_para_clk),
  .cr_para_addr_o          (cr_para_addr),
  .cr_para_sel_o           (cr_para_sel),
  .cr_para_wr_en_o         (cr_para_wr_en),
  .cr_para_rd_en_o         (cr_para_rd_en),
  .cr_para_wr_data_o       (cr_para_wr_data),

  .cr_para_rd_data_i       (cr_para_rd_data),
  .cr_para_ack_i           (cr_para_ack)

);




endmodule
